Hiroshima City University
Graduate School of Information Sciences
Dept. of Computer and Network Engineering
My website is here.
Other affiliation / position
Hiroshima City University Vice President
Tokyo Resarch Laboratory, IBM Japan, limited, Researcher 1984/04/01-1988/06/30
Graduate School of Engineering, Hiroshima University, Associate Professor 1988/07/01-2003/03/31
Hiroshima University Graduate School, Division of Engineering システム工学 Doctor course 1984 Completed
Doctor of Engineering Hiroshima University
Subject of research
Study on VLSI CAD 1988-Present
Efficient Problem Solving for Combinatorial Optimization Problems Using FPGAs 2001-Present
Research paper (international conference proceedings) Joint An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data Toshitaka Ito, Yuri Itotani, Shin’ichi Wakabayashi, Shinobu Nagayama, Masato Inagi Proc. 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2018) 347-352 2018/03/26
Research paper (international conference proceedings) Joint A Programmable Architecture Based on Vectorized EVBDDs for Network Intrusion Detection Using Random Forests Binbin Xue, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi Proc. 2017 International Symposium on Nonlinear Theory and Its Applications (NOLTA2017) 2017/12/04
Research paper (international conference proceedings) Joint Table Reference-Based Acceleration of a Lithography Hotspot Detection Method Based on Approximate String Search Shuma Tamagawa, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi Proc. 10th International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS2017) 10-14 2017/09/10
Research paper (international conference proceedings) Joint An Efficient FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data Yuto Arai, Shin’ichi Wakabayashi, Shinobu Nagayama, Masato Inagi Proc. 2016 International Conference on Field-Programmable Technology IEEE 253-256 2016/12/03 With the recent explosive growth of data in the real world, data mining techniques to obtain characteristics and knowledge from big data attract more attention. This paper focuses on a method to detect outliers in streaming data, and proposes a fast FPGA implementation of outlier detection based on the Mahalanobis distance. The proposed circuit is fully pipelined, and in every clock cycle, a given sample data can be judged as an outlier or not. Experimental evaluation shows that the proposed circuit is 37 times faster than the software implementation of the Mahalanobis distance-based outlier detection.
Research paper (international conference proceedings) Joint A High-Speed Programmable Network Intrusion Detection System Based on a Multi-Byte Transition NFA Tomoaki Hashimoto, Shin’ichi Wakabayashi、 Shinobu Nagayama, Masato Inagi, Hiroki Takaguchi Proc. 9th International Conference on Advances in Circuits, Electronics and Microelecronics IEEE 45-51 2016/07/28 To improve the network security, when a virus pattern is updated, an arbitrary updated pattern should be quickly set in a network intrusion detection system (NIDS). This type of NIDS is called “programmable.” However, present programmable NIDSs could hardly be applied to a high-speed network with more than 10 Gbps of network transmission speed due to the limitation of clock frequency of the circuit. To overcome this speed limitation, this paper proposes a programmable NIDS based on a multi-byte transition nondeterministic finite automaton (NFA). The proposed NIDS is implemented on an FPGA to evaluate its performance. The FPGA implementation results show that the proposed NIDS can achieve more than 10 Gbps of throughput.
第３回LSI IPデザインアワードIP賞 2001/05
広島市立大学高大連携講座 Others 2005/08-2005/08 大学で学ぶということ
広島市立大学情報科学部公開講座 Open lecture 2003/11-2003/11 ナノ世界の大都市建設 － 半導体集積回路はどのように設計されるか －