日本語
Hiroshima City University 
Graduate School of Information Sciences 
Dept. of Computer and Network Engineering 

Professor 
Wakabayashi Shinichi 

 
My website is here.  

Other affiliation / position
Hiroshima City University  Vice President 

Career
Tokyo Resarch Laboratory, IBM Japan, limited, Researcher  1984/04/01-1988/06/30 
Graduate School of Engineering, Hiroshima University, Associate Professor  1988/07/01-2003/03/31 

Academic background
Hiroshima University  Graduate School, Division of Engineering  システム工学  Doctor course  1984  Completed 

Academic degrees
Doctor of Engineering  Hiroshima University 

Subject of research
Study on VLSI CAD  1988-Present 
Efficient Problem Solving for Combinatorial Optimization Problems Using FPGAs  2001-Present 

Bibliography
ワークステーション  1990 
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Papers
Research paper (international conference proceedings)  Joint  An Efficient FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data  Yuto Arai, Shin’ichi Wakabayashi, Shinobu Nagayama, Masato Inagi  Proc. 2016 International Conference on Field-Programmable Technology  IEEE  253-256  2016/12/03  With the recent explosive growth of data in the real world, data mining techniques to obtain characteristics and knowledge from big data attract more attention. This paper focuses on a method to detect outliers in streaming data, and proposes a fast FPGA implementation of outlier detection based on the Mahalanobis distance. The proposed circuit is fully pipelined, and in every clock cycle, a given sample data can be judged as an outlier or not. Experimental evaluation shows that the proposed circuit is 37 times faster than the software implementation of the Mahalanobis distance-based outlier detection. 
Research paper (international conference proceedings)  Joint  A High-Speed Programmable Network Intrusion Detection System Based on a Multi-Byte Transition NFA  Tomoaki Hashimoto, Shin’ichi Wakabayashi、 Shinobu Nagayama, Masato Inagi, Hiroki Takaguchi  Proc. 9th International Conference on Advances in Circuits, Electronics and Microelecronics  IEEE  45-51  2016/07/28  To improve the network security, when a virus pattern is updated, an arbitrary updated pattern should be quickly set in a network intrusion detection system (NIDS). This type of NIDS is called “programmable.” However, present programmable NIDSs could hardly be applied to a high-speed network with more than 10 Gbps of network transmission speed due to the limitation of clock frequency of the circuit. To overcome this speed limitation, this paper proposes a programmable NIDS based on a multi-byte transition nondeterministic finite automaton (NFA). The proposed NIDS is implemented on an FPGA to evaluate its performance. The FPGA implementation results show that the proposed NIDS can achieve more than 10 Gbps of throughput. 
Research paper (scientific journal)  Joint  Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies  Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi  IEICE Transactions on Fundamentals  電子情報通信学会  E98-A/ 12, 2572-2583  2015/12/01 
Research paper (scientific journal)  Joint  An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating  Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi  IPSJ Transactions on System LSI Desigh Methodology  情報処理学会  7, 110-118  2014/08/01 
Research paper (scientific journal)  Joint  シストリックアルゴリズムとNFAに基づくパターン非依存正規表現マッチングハードウェア  若葉陽一, 若林真一, 稲木雅人, 永山忍  電子情報通信学会論文誌D  電子情報通信学会  J96-D/ 10, 2139-2149  2013/10/01 
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Prizes
第3回LSI IPデザインアワードIP賞  2001/05 
米国電気電子学会回路とシステムアジア太平洋会議最優秀論文賞  1992/12 
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Allotted class
Electronic Circuits 
LSI Design Practice 
Advanced Logic Circuits and Systems 
論理設計 
論理設計演習 
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Open lecture
広島市立大学高大連携講座  Others  2005/08-2005/08  大学で学ぶということ 
広島市立大学情報科学部公開講座  Open lecture  2003/11-2003/11  ナノ世界の大都市建設 - 半導体集積回路はどのように設計されるか - 
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